Digital controller for high-frequency switching power supplies

ABSTRACT

A voltage controller ( 150 ), the controller comprising: a voltage comparator ( 700 ) operative to provide a digital error signal ( 152 ); a compensator ( 300 ) operative to determine a digital control signal ( 154 ) based on said provided error signal; and a modulator ( 400 ) operative to provide a power control signal ( 156 ) based on said determined digital control signal, wherein said comparator, said compensator, and said modulator are implemented entirely with digital logic gates.

RELATED APPLICATIONS

The instant application claims the benefit of U.S. Provisional PatentApplication No. 60/338,712, filed 12 Dec. 2001, entitled “DigitalController for High Frequency Switching Power Supplies”, the disclosureof which application is hereby incorporated by reference. This instantapplication also claims priority to U.S. patent application Ser. No.10/291,098 entitled “Adaptive Voltage Regulator for Powered DigitalDevices”, filed 8 Nov. 2002, the disclosure of which application ishereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to voltage control and in particular todigital voltage control for high frequency voltage regulators.

2. Statement of the Problem

Analog voltage controllers are widely used in cooperation with powerconverters for DC-DC (direct-current to direct-current) converters.Analog controllers are fast and can generally be built with widelyavailable analog components. However, the operation of analogcontrollers depends on the precision of the individual componentsincluded therein. Accordingly, considerable effort must be expended toensure selection of analog components adhering to very precise qualitycontrol standards. Moreover, even after such careful selection, thebehavior of analog components is subject to variations in manufacturingprocesses, operating temperatures, and degradation over time. Moreover,analog designs are not readily realized employing existing automateddesign methods. Accordingly, the design of analog controllers tends tobe time-consuming and labor intensive.

Some existing voltage controllers include one or more digitallyimplemented components. However, the digital components implemented inexisting voltage controllers have not performed as desired. For example,digital signal processors (DSPs) have been implemented to performarithmetic operations, such as multiplication, as part of the operationof a compensator, within a voltage controller. However, these DSPimplementations are slow, take up a lot of space, and are excessivelycomplex for the task being performed. Moreover, because the DSPs requiredigital data to operate, their implementation incurs the need for largeand energy-expensive analog to digital converters (ADCs). The ADCsincluded in such controllers are precision analog components which takeup an inordinate amount of valuable space on chips, consume largeamounts of power, and are subject to the same temperature-induced andprocess-induced performance variations as are analog components of theolder existing controllers.

Accordingly, the art of voltage control would benefit from the provisionof a voltage controller which is small, energy and space-efficient, andwhose performance is not dependent of the temperature and processvariations of individual controller components.

SUMMARY OF THE INVENTION

The present invention advances the art and helps to overcome theaforementioned problems by providing a small, fast, accurate,energy-efficient voltage controller, the performance of which isindependent of temperature-variations and other variations in thecharacteristics of component parts. In the preferred embodiment, allfunctions of the inventive controller are implemented employing digitallogic gates, thereby avoiding the need for, and the performancevariations of, precision analog components. In the preferred embodiment,the digital logic gates forming the inventive controller can beeffectively modeled employing existing electronic design automation,such as hardware description languages (HDLs), thereby simplifying andshortening design time.

A delay line ADC, preferably consisting exclusively of digital logicgates, preferably provides a digitally encoded error signal indicativeof a disparity between an output voltage and a reference voltage. Thedelay line ADC disclosed herein thereby preferably performs the functionassociated with analog voltage comparison devices in existing analogcontrollers. Separately, the delay line ADC preferably performs thefunction of a combination of an ADC and a digital voltage comparisondevice in existing partially digitally implemented voltage controllers.

In the preferred embodiment, a hybrid digital pulse width modulator andcompensator are also digitally implemented. In the preferred embodiment,the compensator includes a lookup table for rapidly converting a digitalerror signal from the delay line ADC into a digital control signal,which is preferably a digitally expressed duty ratio, provided as outputfrom the compensator. In the preferred embodiment, a digital pulse widthmodulator receives the compensator-provided digital control signal asinput and converts this digital signal into a duty ratio-controlled timevarying control signal as output from the controller. Preferably, thecontroller output is provided to a power converter to increase ordecrease the regulator output voltage, depending on the results of acomparison between the output voltage and the reference voltage.

The advantages of implementing the digital controller technologydisclosed herein include the following. A fully digital controller couldbe very attractive in high-frequency, low-to-medium power DC-DCconverters because of the inherently lower sensitivity to process andparameter variations, the ready programmability of various controllerperformance characteristics, the reduction or elimination of passivecomponents for tuning, and the ease of integration with other digitalsystems. A benefit arising from compensator programmability and from theabsence of the need to tune passive components is that the samecontroller hardware could be used with a range of power converterconfigurations and power-stage parameter values. In addition, withdigital controller implementation, it is possible to implement controlschemes that are impractical for analog controller designs.

For example, it is desirable to have the ability to precisely matchphase-shifted duty ratios to a simple, robust control for voltageregulator modules (VRMs) using a dedicated digital controller IC(integrated circuit). In transformer-isolated DC-DC converters, digitalsignal transmission through the isolation can be used to address limitedbandwidth and/or large gain variations associated with standard analogapproaches. In general, more sophisticated control methods could be usedto achieve improved dynamic responses.

Another advantage of the digital approach is that well established andautomated digital design approaches can be applied. A controller designmay be described at the functional level using a hardware descriptionlanguage (HDL). Preferably, synthesis, simulation, and verificationtools are available to target the design to implementation to standardcell ASICs (application-specific integrated circuits) or FPGAs (fieldprogrammable gate arrays) from the HDL description. The design can thenbe implemented employing different manufacturing processes, integratedwith other digital systems, or modified to meet updated specifications.In contrast to analog IC controller realizations, the digital controllerdesign preferably scales well, and can thus take advantage of advancesin fabrication technologies, without design alteration.

The above and other advantages of the present invention may be betterunderstood from a reading of the following description of the preferredexemplary embodiments of the invention taken in conjunction with thedrawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a voltage regulator including a digitalvoltage controller according to a preferred embodiment of the presentinvention;

FIG. 2 is a plot of the transient response of output voltage and outputcurrent obtained with the regulator of FIG. 1;

FIG. 3 is a block diagram of the operation of the digital voltagecontroller of FIG. 1;

FIG. 4 is a block diagram of the pulse width modulator included in thedigital voltage controller of FIG. 1;

FIG. 5 is a plot of waveforms of signal values of the pulse widthmodulator of FIG. 4;

FIG. 6 is a plot of duty ratio output as a function of digital input forthe pulse width modulator of FIG. 4;

FIG. 7 is a block diagram of the delay line ADC included in the voltagecontroller of FIG. 1;

FIG. 8 is a schematic diagram of a delay cell ADC corresponding to thedelay cells included in the delay line of FIG. 7;

FIG. 9 is a plot of timing waveforms for tap signals of the delay lineADC of FIG. 7;

FIG. 10 is a plot of the conversion characteristic of the delay line ADCof FIG. 7;

FIG. 11 is a block diagram of a preferred digital calibration scheme forthe delay line ADC of FIG. 7;

FIG. 12 is a plot of timing waveforms of the calibration scheme of FIG.11;

FIG. 13A is a plot of the measured load voltage regulation against loadcurrent for the voltage regulator of FIG. 1;

FIG. 13B is a plot of the measured load voltage regulation againstsupply voltage for the voltage regulator of FIG. 1; and p

FIG. 14 is a block diagram of the function of encoder 730 included inthe delay line ADC 700 of FIG. 7.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In this disclosure, a transistor terminal is either the source or drainof a field effect transistor (FET) or the emitter or collector of abipolar junction transistor (BJT). Herein, a comparator is any devicethat receives two voltage values and which provides as output a signalindicative of a difference between the two received voltage values.Herein, the terms “comparator” and “voltage comparator” are usedinterchangeably. In this disclosure, energy-storing components includeboth analog and digital devices, including for instance, capacitors,inductors and powered digital logic gates. The term “energy-storingcomponents” is intended to exclude wiring and other conductive apparatusoperative merely to connect one electronic component to another. Herein,a resistor is a device having resistance concentrated in a lump form.Herein, a resistor does include wiring or other conductive links betweenelectronic components. Herein, an electronic memory is a digitalelectronic storage device able to supply stored values in response to anidentification of an address in the electronic memory of the storedvalues. Herein, a digital electronic calculator may include a digitalelectronic storage device and/or digital devices for performingarithmetic operations including any one or more of addition,subtraction, multiplication, and/or division.

Herein, a signal tap array may include any number of signal taps. Asignal tap array preferably includes a plurality of signal taps, eachtap connected to one delay cell within an array of delay cells. However,a signal tap array may include signal taps connected to only a subset ofdelay cells within a delay cell array. Herein, binary digital code isconventional digital code in which a sequence of bits identifiescoefficients of values equal to number “2” raised to different powers.For example, digital code “101” corresponds to 1·1+0·2+1·4=5. Binarydigital code is distinguished from “thermometer code” in which each bitin a sequence is of equal numerical weight.

FIG. 1 is a block diagram of a voltage regulator 100 including a digitalvoltage controller 150 according to a preferred embodiment of thepresent invention. Regulator 100 preferably includes power converter 200and controller 150. Power converter (“converter”) 100 is preferably asynchronous buck converter. Power converter preferably includes gatedriver 204 which is connected to the gate of transistor switch 202, afirst terminal of which transistor is connected to supply voltage 102positive node 114 and a second terminal of which is connected to node116. Gate driver 206 provides an output connected to the gate oftransistor switch 208, one terminal of which transistor is connected tosupply voltage negative node 112 and the other terminal of which isconnected to node 116. Inductor 210 is preferably located between node116 and node 118. Capacitor 212 is preferably located between node 118and node 112.

In the embodiment of FIG. 1, power converter 200 is connected to supplyvoltage V_(g) 102 and produces output voltage V_(o) 104 which isconnected between node 118 and node 112 of converter 200 across load110, which is connected in parallel with capacitor 212. The operation ofconverter 200 is known in the art and is therefore not discussed indetail in this disclosure. It will be appreciated that the presentinvention is not limited to the design of converter 200. A wide range ofdesigns and principles of operation may be incorporated into converter200 which would not affect the operation of the preferred embodiment ofcontroller 150. It will be appreciated that converter 200 of FIG. 1 ismerely one of many converter designs which could be employed inconjunction with controller 150.

In the preferred embodiment, controller 150 includes delay line ADC 700,compensator 300, and pulse width modulator (PWM) 400, which ispreferably a hybrid digital pulse width modulator. Preferably, voltagesV_(sense) 108 and V_(ref) 106 are inputs to controller 150, and, inparticular, to delay line ADC 700. Equipment (not shown) for providingV_(ref) 106 is preferably not part of controller 150. Preferably,external memory 160 is available to supply information to compensator300, when needed. Delay line ADC 700 preferably serves as a voltagecomparator in the embodiment of FIG. 1. While delay line ADC 700 is thepreferred voltage comparator in the present application, the currentinvention is not limited to the use of delay line ADC 700 for generationof a signal indicative of a voltage difference between voltagesV_(sense) 108 and V_(ref) 106. In alternative embodiments, a range ofdevices, either analog or digital, for providing a signal indicative ofa voltage difference between two voltage sources may be employed incontroller 150, and all such variations are intended to be includedwithin the scope of the present invention.

In this embodiment, converter 200 and controller 150 form a closed-loopfeedback system 100, to preferably regulate output voltage V_(o) 104 tomatch a stable voltage reference V_(ref) 106 (or a scaled version of thereference) over a range of input voltage 102 values and load currents,and over a range of process and temperature variations. In thisembodiment, output voltage 104 is sensed and compared to V_(ref) 106.Digital error signal 152 is preferably transmitted to compensator 300.Compensator 300 output (digital control signal) 154 is the input topulse width modulator 400, which in turn preferably produces a constantfrequency variable duty ratio signal (power control signal) 156 tocontrol the switching power transistors 202, 208. The preferredembodiment of a digital controller architecture to implement thiscontrol scheme is shown in FIG. 3.

Preferably, V_(sense) 108 is a scaled version of Vo 104. Expressing thismathematically, we have V_(sense)=HV_(o). However, in this disclosure,for the sake of simplicity, H is considered to have a value of 1. Thus,for the remaining discussion, V_(sense) 108 and V_(o) 104 have the samevalue. Preferably, Vo 104 is sampled by an A/D (analog to digital)converter to produce digital error signal e(n) 152. Preferably, samplingof Vo 104 occurs once per switching period T_(s). Here, the index valueof “n” refers to the current switching period.

Generally, effective voltage regulation generally requires that V_(o)(t)104 remain within a defined range of V_(ref) 106, fromV_(ref)−(ΔV_(o))_(max)/2 to V_(ref)+(ΔV_(o))_(max)/2. Otherwise stated,the permissible range for steady-state output voltage 104 isV_(o)=V_(ref)±ΔV_(o)/2. To maintain Vo 104 within the permissible range,the analog equivalent of the least significant bit (LSB) in the A/Dcharacteristic should not be greater than the desired magnitude ofΔV_(o). Preferably, the specifications for ΔV_(o) and (ΔV_(o))_(max) aresuch that only a few digital values are needed to represent themagnitude of the analog voltage error, which is equal to V_(ref)106−V_(sense) 108.

FIG. 3 is a block diagram of the operation of digital voltage controller150 of FIG. 1. In the embodiment of FIG. 3, the digital representationof error signal 152 assumes one of nine values, from −4 to +4 (decimal).Although ADC 158 preferably has sufficiently fine resolution toaccurately regulate Vo 104, only a few bits are needed to representdigital error signal e(n) 152. In the preferred embodiment, the value ofdigital error signal 152 is used as a lookup table address. Thus, anyarbitrary association may be established between the magnitude ofdigital error signal 152 and the magnitude of the numerical entrieslocated at the lookup table address pointed to by the digital errorsignal 152 value. Table 1, located later in this document, identifies apreferred embodiment correlation between digital error signal values andthe magnitude of the control signal desired. Herein, the “digital errormagnitude” is a value that corresponds to the magnitude of the disparitybetween the measured voltages. Preferably, a digital error signalcorresponds to the lookup table address at which its digital errormagnitude is located.

A novel delay line ADC configuration 700 that takes advantage of therequired static A/D characteristic and which lends itself to a simpledigital implementation is described in connection with FIG. 7. It willbe appreciated that delay line ADC 700 is the preferred although not theonly available embodiment of ADC 158.

In addition to relaxing the requirements for ADC 158, the ability torepresent error signal 152 with a limited number of bits enables asimplified implementation of the next controller component—compensator300. Preferably, compensator 300 uses the value of digital error signal152, optionally along with stored values of signal 152 from previouscycles, to calculate a digital control signal 154, which in thepreferred embodiment, is a digitally expressed duty ratio of a constantfrequency signal.

The computation within compensator 300 may be established in accordancewith established digital control theory. However, standardimplementation of linear control laws in compensator 300 would generallyinvolve the use of digital adder(s) and/or digital multiplier(s), whichdevices increase the size of controller 150 and which tend to increasethe clock frequency requirements for controller 150. To beneficiallyexploit the fact that only a small number of bits are needed torepresent digital error signal 152, the preferred embodiment ofcompensator 300 instead calculates duty ratio 154 using look-up tables302, 304, and 306 and adder 318. Preferably, the current and theprevious values of digital error signal 152 serve as address(es) fromwhich values may be obtained in lookup tables 302, 304, and 306. Sincedigital error signal 152 preferably assumes only a small number ofvalues, the number of entries in the lookup tables 302, 304, and 306 iscorrespondingly small. Consequently, the implementation of tables 302,304, and 306 requires only minimal real estate on a chip. Moreover, thecalculation of duty ratio 154 can preferably be accomplished in a smallnumber of system clock 120 cycles. Although the discussion of FIG. 3 isdirected to an embodiment including three lookup tables and one adder,it will be appreciated that more than one adder could be employed andthat fewer or more than three lookup tables could be employed.

Preferably, compensator 300 can be programmed to perform differentcontrol algorithms by adjusting the values of entries in lookup tables302, 304, and 306. One control algorithm supported in the embodiment ofFIG. 3 is described as follows:

(1) d(n+1)=d(n)+α(e(n))+β(e(n−1))+γ(e(n−2)), where α(•), β(•) and γ(•)may be either linear or nonlinear functions of digital error signal 152.However, a variety of control algorithms can be implemented. Oneadditional example is described by:

(2) d(n+1)=d(n)+ae(n)+be(n−1)+ce(n−2),

where a, b, and c are constants and corresponds to a basic PID(proportional, integral, and derivative) control algorithm. In thedesign of controller 150, once the coefficients a, b and c are selected(to achieve a desired closed-loop bandwidth and adequate phase margin,for example), the products a·e, b·e, and c·e are preferably pre-computedfor all possible values of the error “e” and preferably programmed intolookup tables 302, 304, and 306 from external memory 160. As analternative to using external memory 160, lookup tables 302, 304, and306 could be preprogrammed and hard-wired on the chip at design time, orprogrammed from other system components via a suitable interface at runtime. Thus, external memory 160 is one beneficial approach to supplyingdata to lookup tables 302, 304, and 306, but alternatives approaches, asdiscussed above, are available.

The programmability of compensator 300 preferably enables the samecontroller 150 hardware to be used with different power-stageconfigurations and different power-stage parameters by modifying dataentries to lookup tables 302, 304, and 306 rather than by makinghardware changes. Moreover, compensator 300 preferably enablesexperimentation with various nonlinear control algorithms withoutrequiring the labor-intensive, time-consuming, and inconvenientreplacement of precise analog components.

FIG. 4 is a block diagram of pulse width modulator 400 included in thedigital voltage controller of FIG. 1. FIG. 5 is a plot of waveforms ofvarious signal values of the pulse width modulator of FIG. 4. Pulsewidth modulator (PWM) 400, which is preferably a hybrid digital PWM,preferably completes the controller architecture. PWM 400 preferablyproduces the periodic waveform c(t) 156 from duty ratio 154 andpreferably controls transistor switches 202 and 208 in power converter200 therewith. Preferably, PWM 400 may be beneficially employed toachieve high switching frequency operation and control of Vo 104 withina small, defined range.

PWM 400 preferably operates as a D/A converter (DAC) in voltageregulator 100. Generally, the PWM 400 resolution determines theavailable set of output voltage 104 values. If the PWM 400 resolution isnot sufficiently high, an undesirable limit-cycle oscillation in thevalue of Vo 104 can result. If none of the achievable output voltages104 fall into the range of ΔV_(o) around V_(ref) 106, duty ratio 154will generally oscillate between two or more values. Avoidance of thislimit-cycle operation may be achieved by ensuring that the outputvoltage increment that corresponds to the least-significant bit of dutyratio 154 is smaller than ΔV_(o). This condition has been evaluated as afunction of the steady state input and output voltages for differentconverter configurations.

A high-resolution, high-frequency digital pulse-width modulator (DPWM)can be constructed using a fast-clocked counter and a digitalcomparator. To achieve n-bit resolution at the switching frequencyf_(s), the desired clock frequency is 2^(n)f_(s). This desired clockfrequency generally leads to more demanding timing constraints andincreased power consumption. For example, an 8-bit resolution at theswitching frequency of f_(s)=1 MHz would require a clock frequency of256 MHz. It has been shown that fine time resolution and much lowerpower consumption can be achieved using a tapped delay-line schemesimilar to a ring oscillator that operates at the switching frequency.However, this implementation requires a larger-area digital multiplexer.The PWM architecture selected for use in the preferred embodiment isbased on a hybrid delay-line/counter approach. In this approach, n-bitresolution is achieved using an n_(c)-bit counter (where n_(c)<n),whereas the remaining n_(d)=n−n_(c) bits of resolution are obtained froma tapped delay line.

The embodiment of FIG. 4 is a PWM 400 where 4-bit (n=4) resolution isobtained using 2-bit counter (n_(c)=2) 406 and a 4-cell ring oscillator(n_(d)=2, 2^(n) _(d)=4) 402 which includes flip-flops 416, 418, 420, and422 operating as delay cells. Preferably, at the beginning of aswitching cycle, output SR flip-flop 410 is set, and the PWM 400 outputpulse c(t) 156 goes high. Preferably, a pulse propagates throughoscillator 402 at a frequency of 2^(nc)f_(s)=4f_(s) which pulse servesas the clock pulse for the counter 406. The switching period ispreferably divided into 2^(n) _(d)2^(n) _(c)=16 slots. Preferably, whencounter 406 output matches the top n_(c) 452 most significant bits ofdigital input 154 and a pulse reaches the tap selected by the n_(d) 450least significant bits of digital input 154, output flip-flop 410 isreset, and the output pulse goes low.

It will be appreciated that resolution employing any number of bits n450 may be employed, including a wide range of values for n_(c) 452 andn_(d) 454 may be employed. Preferably, a “pulse-on” period during whichoutput pulse 156 (power command signal) is on corresponds to the valueof digital input 154. This “pulse-on” duration is preferably the productof the duty ratio, expressed by digital input 154, and the switchingperiod (reciprocal of f_(s), the switching period). In order to avoidthe very high clock frequencies needed to accurately establish thepulse-on period with high resolution using only a counter andcomparator, the pulse-on period is preferably established by separatelyestablishing two separate components of the pulse-on period. For a givenswitching period, determination of the first and second components ofthe pulse-on period for output signal 156 effectively determines thefirst and second components of the duty ratio for output signal 156.

In the preferred embodiment, a first component, or first portion, of thepulse-on period is preferably established using a selection n_(c) 452 ofthe highest ordered bits of digital input 154. Counter 406 preferablycounts to a value equal to “2” raised to the power n_(c) 452 at clockfrequency 120. A second component, or second portion, of the pulse-onperiod is preferably established using the n_(d) 454 lowest ordered bitsof the original n 450 bits of digital input 154. The second component ofthe pulse-on period is preferably established using a delay line 402having a specified number of flip-flops. The number of flip-flops usedis preferably equal to 2 raised to the power n_(d) 454. Preferably, themagnitude of the digital value of the sequence of n_(d) 454 bitsdetermines the number of flip-flop delays which form the secondcomponent of the pulse-on period. This hybrid (combination of counterand delay line) approach preferably avoids the need for an extremelyhigh frequency for counter 406 while still maintaining high accuracy forthe resulting pulse-on period during which output signal c(t) 156 ishigh.

In the exemplary waveforms of FIG. 5, the duty ratio of the output pulseis 11/16. The basic delay cell in ring oscillator 402 of FIG. 4 consistsof a single resettable flip-flop. Preferably, the delay of each of cells416, 418, 420, and 422 and the number of cells in ring 402 determine theswitching frequency f_(s). To adjust the switching frequency, any cellof cells 416, 418, 420 and 422 can be modified by inserting additionaldelay elements between the output of a cell and the input to asucceeding cell. The additional delay elements can be standard logicgates, or gates with adjustable delay, if switching frequency tuning orsynchronization with an external clock are desired.

The self-oscillating DPWM (digital pulse width modulator) embodimentshown in FIG. 4 has several desirable properties including a simple HDLdescription, an even number of time slots in a period, an ability tostop and restart the oscillations on command (by gating the propagationof the signal through the ring), and relatively small size. Anexperimental prototype chip was designed in which the DPWM had 8-bitresolution (n=8) using a 3-bit counter (n_(c)=3) and a 32-cell long ring(n_(d)=5). PWM 400 preferably operates at a switching frequency off_(s)=1 MHz. The ring preferably oscillates at 2^(nc)f_(s)=8 MHz. This 8MHz signal is preferably used as the system clock for the entire chip.Experimental results for PWM 400, depicted in FIG. 6, show the measuredduty ratio of the output pulses as a function of 8-bit digital input154. The minimum (3.1%) duty ratio and the maximum (97.3%) duty ratioare preferably established during a design phase.

Generally, static and dynamic output voltage regulation capabilitiesdepend on the characteristics of the A/D converter employed.Conventional, high-speed, high-resolution A/D converters consume powerand chip area, and require precision analog components. Also, in aswitching power supply, the sensed analog voltage signal is provided bya switching power converter. This signal generally has a lot ofswitching noise, which can be a problem for many conventional A/Dconverters such as the basic flash configuration. Accordingly, theinventors sought an alternative ADC embodiment, which is described belowin connection with FIG. 7.

FIG. 7 is a block diagram of delay line ADC 700 preferably forming partof voltage controller 150 of FIG. 1. FIG. 8 is a schematic diagram ofdelay cell ADC 800 corresponding to the delay cells 710, 712, 714, 716,and 718 included in the delay line ADC 700 of FIG. 7. Timing waveformsembodiment of delay-line ADC 700 embodiment of FIG. 7 are shown in FIG.9. In this disclosure, the designation “delay cell 800” will be usedwhen referring to a delay cell in general. Where a particular delay cellis indicated, the reference numeral designating that delay cell will beemployed. Preferably, each delay cell 800 has an input 804, an output810, and a reset input R 812. Preferably, when reset input 812 is activehigh, cell output 810 is reset to zero. In the preferred embodiment, anarray 740 of delay cells (preferably comprising logic gates) 800receives sensed analog voltage 108. Thus, V_(sense) 108=V_(DD) for eachcell in array 740.

The preferred embodiment of delay-line ADC 700 converter is based on theprinciple that the propagation delay of a CMOS-type (complementary metaloxide semiconductor) logic gate increases if the gate supply voltage isreduced. To the first order, the propagation delay t_(d) of a signalthrough a CMOS logic gate as a function of the supply voltage V_(DD) isgiven by: $\begin{matrix}{{t_{d} = {K\frac{V_{DD}}{\left( {V_{DD} - V_{th}} \right)^{2}}}},} & (3)\end{matrix}$where V_(th) is the CMOS device threshold voltage, and K is a constantthat depends on the device/process parameters, and the capacitiveloading of the gate. Clearly, increasing V_(DD) results in shorterpropagation delay. For supply voltages higher than the threshold V_(th),the delay is approximately inversely proportional to V_(DD).

To perform a conversion, at the beginning of a switching cycle, testsignal 704 is propagated through cell array 740. After a fixedconversion-time interval, which is preferably equal to (6/8)T_(s) in theexample waveforms of FIG. 9, taps t₁ 728 to t₈ 736 are preferablysampled by “sample” signal 738 which is preferably the clock pulse forthe series 750 of D-type flip-flops 720, 722, 724, and 726. The resultat flip-flop outputs q₁ 752 to q₈ 758 is preferably communicated todigital encoder 730 to produce digital error signal 152. Preferably, thelast portion of the switching cycle is used to reset all cells in delayline 700, to prepare for the next conversion cycle.

As V_(sense) 108 increases, cell delay t_(d) decreases, and test pulse704 propagates further within cell array 740. Conversely, As V_(sense)108 decreases, cell delay t_(d) increases, and test pulse 704 propagatesto fewer cells 800 within cell array 740. The sampled tap outputs (q₁ toq₈) give the A/D conversion result in “thermometer” digital code. Forexample, for the case illustrated by the waveforms 900 of FIG. 9, thetest pulse propagates to the taps t₁ through t₆, but not to the taps t₇and t₈, such that the sequence 770 of flip-flop digital outputs (q₁, q₂,, q₈) equals: 11111100.

Ideally, V_(sense) 108 equals V_(ref) 106, and test pulse 704 propagatesto the first half 760 of the tapped delay cells. In the embodiment ofFIG. 7, this zero-error case corresponds to the flip-flop outputsequaling (q₁, q₂, q₃, q₄, q₅, q₆, q₇, q₈)=11110000. Preferably, encoder152 converts the sequence of flip-flop outputs 770 into digitalinformation encoded in a more useful form. In the preferred embodiment,this more useful form is digital error signal 152.

In the preferred embodiment, digital error signal 152 provides a valueindicative of the difference, or error, between V_(sense) 108 andV_(ref) 106. The desired steady state operation of the power supplycorresponds to a digital error signal 152 value of zero. Preferably,encoder 730 provides a digital error signal 152 having a digital value,the magnitude of which is proportional to the analog voltage differencebetween V_(sense) 108 and V_(ref) 106. Table 1 and the discussion belowexpand on the function of encoder 730. The “digital error magnitude” wasdiscussed earlier in this disclosure. For the sake of consistency ofterminology, the term “digital error magnitude” is included in Table 1.However, the entries in the table are expressed in decimal form forconvenience. TABLE 1 Delay line specifications. Thermometer DigitalError Encoder 730 Vsense Range Code Magnitude output Vsense < 2.3811111111 +4 0000 2.38 <= Vsense < 2.42 01111111 +3 0001 2.42 <= Vsense <2.46 00111111 +2 0010 2.46 <= Vsense < 2.50 00011111 +2 0011 2.50 <=Vsense < 2.54 00001111 +1 0100 2.54 <= Vsense < 2.58 00000111 0 01012.58 <= Vsense < 2.62 00000011 −1 0110 2.62 <= Vsense < 2.66 00000001 −20111 2.66 <= Vsense 00000000 −3 1000

FIG. 14 is a block diagram of the function of converter 730 included inthe delay line ADC 700 of FIG. 7. In the preferred embodiment, encoder730 accepts the delay line ADC 700 thermometer code 772 as input andoutputs encoded digital output 152. Thermometer code 772 is the sequenceof digital values included in sequence 770 of flip-flop outputs.Thermometer code is preferably directed to differentiator block 774which differential vector 776 and overflow indicator 778 to encoderblock 784. Encoder block thereafter provides digital output 152.

The second and third columns of Table 1 specify the input to and outputfrom encoder 730. Since this is a simple binary translation from oneencoding scheme to another, the encoder can be implemented usingbehavioral HDL and synthesis techniques. However, other conversionmechanisms may be employed. It will be appreciated that the data intable 1 is exemplary. Different voltage ranges of Vsense may beassociated with the digital values in columns 2 and 3 for one or more ofthe entries in table 1.

In the preferred embodiment of delay line ADC 700, the length of thedelay cell array 740 effectively determines the reference voltage valuearound which the analog to digital conversion characteristic iscentered. The number of cells 800 and the delay of each cell 800preferably determine the range (ΔV_(o))_(max) and the effective LSBvoltage resolution of the delay line ADC 700. In an experimentalprototype chip, the delay-line length and the cell delay were designed(by simulation) to have values V_(ref)≈2.5V, and ΔV_(o)≈40 mV. Eightcells 800, each with associated taps, preferably provide an A/D voltageconversion range (ΔV_(o))_(max)=(8+1)ΔV_(o)≈360 mV.

Some advantages of the preferred delay-line ADC 700 are that its basicconfiguration does not require any precision analog components and thatit can be implemented using standard digital logic gates. Therefore,delay line ADC 700 scales well and can be based on an HDL description.When using delay line ADC 700, sampling at high switching frequencies(in the range from hundreds of KHz to several MHz) can be readilyaccomplished using integrated circuits made using modern sub-micron CMOSprocesses. Moreover, the preferred embodiment of delay line ADC 700 hasbuilt-in noise immunity, which noise immunity arises from the fact thatthe sampling can extend over a large portion of the switching periodover which the input analog signal V_(sense) 108 is effectivelyaveraged. Therefore, digital output 152 is preferably not affected bysharp noise spikes in the output voltage 104 of power converter 200.

The conversion characteristic 1000 measured for a prototype versiondelay line ADC 700 is shown in FIG. 10. The shaded portions of thecharacteristic (plot) 1000 indicate voltages for which digital outputcode 152 may assume one of two consecutive values. Characteristic 1000exhibits some non-linearity but is monotonic. And, the widths of thecode “bins” are approximately equal to the desired ΔV_(o) value. In avoltage regulator application, the A/D imperfections (code-flipping andnon-linearity) have very little effect on the closed-loop operation.During steady state operation, output voltage 104 preferably convergeson a voltage corresponding to a digital error signal 152 value of zero.On a set of 10 prototype chips, the inventors found the average of thezero-error bin width to be equal to 53 mV, with a standard deviation of3.6 mV. The measured reference voltage was V_(ref)=2.7 V, while themeasured current consumption of the delay line ADC 700 was about 10 μA.

The basic delay-line ADC 700 results in a reference voltage V_(ref) 106that is indirectly determined by the length of the delay line 700 and bythe delay-versus-voltage characteristic of each delay cell 800. Inpractice, because of process and temperature variations, the referencevalue obtained by the basic delay-line A/D configuration is difficult toprecisely control. Variation of the effective V_(ref) 106 causesvariation in the regulated output voltage 104, and this variation couldcause regulator 100 to perform sub-optimally. Accordingly, delay lineADC 700 is preferably calibrated prior to being implemented in anoperating voltage regulator 100. Otherwise stated, the extent of delayin delay line ADC 700 is preferably correlated with known voltagevalues. This established correlation is preferably employed during lateroperation of controller 150 to reliably associate an extent of testpulse 704 signal propagation delay along delay cell array 740 with aparticular voltage.

FIG. 11 is a block diagram of a preferred digital calibration scheme1100 for delay line ADC 700 of FIG. 7; and FIG. 12 is a plot of timingwaveforms of the calibration scheme 1100 of FIG. 11. A preferredcalibration approach involves applying a stable, precise referencecalibration reference voltage 1102, preferably generated using standardbandgap techniques, to the input 782 of delay line ADC 700 and todigitally subtract the conversion result from the digital output 152value obtained when the actual analog input voltage V_(sense) 106 isapplied. Calibration reference voltage 1102 may, but need not, be thesame as reference voltage 106 discussed in connection with FIGS. 1, 3,and 7.

In the preferred embodiment, two conversions are performed in eachswitching period. In one half of the switching period, the calibrationreference voltage V_(ref) 1102 is preferably applied to delay line ADC700. The result of the reference conversion e_(ref) 1108 ideally 0, butthe actual value can have finite magnitude because of process andtemperature variations. Reference conversion error value e_(ref) 1108 ispreferably stored in register 1106. In the second part of the period,V_(sense) 108 is preferably applied to delay line ADC 700. Preferably,delay line ADC 200 provides an un-calibrated digital output 152, asdescribed in connection with FIG. 7, corresponding to the analog voltagevalue of V_(sense) 108. Thereafter, un-calibrated output 152 ispreferably subtracted from e_(ref) 1108 to obtain calibrated digitaloutput 1152. In the preferred embodiment, where calibration is employed,calibrated digital output 1152 is used instead of uncalibrated digitaloutput 152, thereby providing greater accuracy for correction of outputvoltage V_(o) 104. Herein, the terms “calibrated digital output”,“corrected digital output”, “calibrated digital error signal”, and“corrected digital error signal” are used interchangeably.

The generation of the reference conversion error value 1108 may, butneed not, be conducted in each switching period. An appropriatefrequency of reference conversion may be selected based on thecharacteristics of a particular voltage controller 150. Separately,other calibration schemes may be implemented in conjunction with thepresent invention including but not limited to schemes based ondelay-locked loop (DLL) principles.

Controller 150, described herein, was designed and implemented in astandard 0.5μ (micron) CMOS process. The chip design was described usingHDL. Synthesis and timing verification tools were used to reduce thedesign to standard cell gates. A preferred embodiment of delay line ADC700 occupies less than 0.2 mm² (square millimeters). The total activechip area for controller 150 is preferably less than 1 mm².

In the preferred embodiment, compensator 300 includes 3 tables (fore(n), e(n−1), and e(n−2)). Preferably, digital error signal 152generated by delay line ADC 700 can have 9 possible values. In thepreferred embodiment, the outputs from lookup tables 302, 304, and 306have 8 bits, 9 bits, and 8 bits, respectively. Therefore, the totalon-chip memory storage is preferably 234 bits. However, it will beappreciated, that in alternative embodiments, the number of tables incompensator 300, the number of bits in the lookup tables, the number ofpossible values of digital error signal 152, and the total number ofbits in on-chip memory storage may be lower than or greater than thenumbers of these items disclosed in the preferred embodiment describedabove.

In the preferred embodiment, the bit-lengths of the table entries aredetermined by the range of error signal 152 values (±4) and by thedesired precision of pole-zero placement. Adder 318 preferably producesa 10-bit signed value which is preferably reduced to 8-bit duty ratiosignal 154 by eliminating the sign bit, and by truncating the leastsignificant bit.

To demonstrate closed-loop operation of the preferred embodiment, thecontroller chip was used with a synchronous buck converter as shown inFIG. 1. The input voltage V_(g) 102 was set between 4 V and 6 V, theoutput voltage 104 was regulated at V_(o)=2.7V, the load current was setbetween 0 A and 2 A, and the switching frequency was set to 1 MHz. Thefilter components used had values of L 210=1 μH (micro-Henry) and C212=100 μF (micro-Farads). Based on the standard averaged model ofconverter 200, compensator 300 was designed using the pole-zero matchedmethod to achieve a loop cross-over frequency of approximately 50 KHzand a phase margin of about 50°. When converter 200 is powered up, itloads compensator 300 table entries from external memory 160 and thenstarts to sample output voltage 104 and to produce pulsating waveformc(t) 156.

FIG. 2 is a plot of the transient response of output voltage 104 andoutput current obtained with regulator 100 of FIG. 1. Experimental50%-100% load transient waveforms are shown in FIG. 2. In the preferredembodiment, V_(o) 104 remains within the (ΔV_(o))_(max) range 202. FIG.13A is a plot of the measured load voltage 104 against load current forvoltage regulator 100 of FIG. 1. FIG. 13B is a plot of the measured loadvoltage 104 against supply voltage 102 for voltage regulator 100 of FIG.1.

There has been described a novel digital voltage controller. It shouldbe understood that the particular embodiments shown in the drawings anddescribed within this specification are for purposes of example andshould not be construed to limit the invention, which will be describedin the claims below. Further, it is evident that those skilled in theart may now make numerous uses and modifications of the specificembodiments described, without departing from the inventive concepts. Itis also evident that the methods recited may in many instances beperformed in a different order; or equivalent structures and processesmay be substituted for the various structures and processes described.Consequently, the invention is to be construed as embracing each andevery novel feature and novel combination of features present in and/orpossessed by the invention herein described.

1. A voltage controller comprising a compensator, including a lookuptable for determining a digital control signal based on a digital errorsignal; a modulator operative to provide a power control signal inresponse to said determined digital control signal; and a delay lineanalog to digital converter operative to compare a converter voltage toa reference voltage and generate said digital error signal indicative ofa difference between said compared voltages.
 2. The controller of claim1 wherein said controller includes no passive electronic components. 3.The controller of claim 1 wherein said comparator is implementedentirely with digital logic gates.
 4. The controller of claim 1 whereinall energy-storing components in said controller are digital logicgates.
 5. (canceled)
 6. The controller of claim 1 wherein said delayline ADC comprises a delay cell array.
 7. The controller of claim 1wherein said delay line ADC is operative to provide a thermometer codeoutput indicative of said difference between said compared voltages. 8.The controller of claim 7 wherein an extent of test signal propagationthrough said delay line ADC establishes said thermometer code.
 9. Thecontroller of claim 7 wherein said delay line ADC comprises an encoderoperative to convert said thermometer code into said digital errorsignal. 10-15. (canceled)
 16. The controller of claim 1 wherein saidmodulator is a digital pulse width modulator.
 17. The controller ofclaim 1 wherein said modulator comprises a counter operative todetermine a first component of a pulse-on period for said power controlsignal.
 18. The controller of claim 1 wherein said modulator comprises adelay line operative to determine a second component of a pulse-onperiod for said power control signal.
 19. The controller of claim 1wherein said modulator comprises: a counter operative to determine afirst component of a pulse-on period for said power control signal; anda delay line operative to determine a second component of said pulse-onperiod for said power control signal.
 20. An analog to digital converter(ADC) having an input voltage, said ADC comprising: an array of delaycells, each powered by said input voltage; and a signal tap arraycoupled to said delay cell array.
 21. The ADC of claim 20 wherein saiddelay cells are digital logic gates.
 22. The ADC of claim 20 whereinsaid ADC includes no passive analog components.
 23. The ADC of claim 20wherein a speed of test signal propagation through said delay cell arrayis substantially proportional to a magnitude of said input voltage. 24.The ADC of claim 23 wherein said signal tap array comprises a signal tapcoupled to each said delay cell.
 25. The ADC of claim 24 whereinstatuses of said signal taps are indicative of said signal propagationspeed through said delay cell array.
 26. The ADC of claim 20 furthercomprising an encoder for converting thermometer code from said signaltap array into a digital error signal.
 27. The ADC of claim 20 whereinsaid ADC includes no capacitors or inductors.
 28. The ADC of claim 20wherein said ADC includes no capacitors, inductors, or resistors.
 29. Avoltage controller, the controller comprising: a voltage comparatoroperative to compare an analog voltage to an analog reference voltageand provide a digital error signal indicative of a difference betweensaid output and reference voltages; a compensator operative to determinea digital control signal based on said provided error signal; and amodulator operative to provide a power control signal based on saiddetermined digital control signal, wherein said comparator, saidcompensator, and said modulator are implemented entirely with digitallogic gates.
 30. The voltage controller of claim 29 wherein all of saiddigital logic gates correspond to standard library cells.
 31. Thevoltage controller of claim 29 wherein all of said digital logic gatesare HDL (hardware description language)-compatible.
 32. The voltagecontroller of claim 29 wherein said controller includes no passiveelectronic components.
 33. The voltage controller of claim 29 whereinsaid controller includes no analog energy storage components.
 34. Thevoltage controller of claim 29 wherein said controller includes nocapacitors, inductors, or resistors.
 35. A method for controllingvoltage, the method comprising: comparing a converter output voltagewith a reference voltage; generating a digital error signal indicativeof a result of said comparing; and providing a power control signalindicative of said generated error signal, wherein said comparing, saidgenerating, and said providing are performed entirely with digital logicgates.
 36. The method of claim 35 wherein said comparing comprisespowering a plurality of an array of delay cells with said converteroutput voltage.
 37. The method of claim 35 wherein said comparingcomprises measuring an extent of test signal propagation through anarray of delay cells, said delay cells being powered by said converteroutput voltage.
 38. The method of claim 35 wherein said providingcomprises determining a digital control signal from said generated errorsignal according to a control algorithm.
 39. The method of claim 38wherein said determining comprises selecting a lookup table entry basedon a value of said generated error signal.
 40. The method of claim 35wherein said providing comprises determining a duty ratio from saidgenerated error signal according to a control algorithm.
 41. A method ofcontrolling voltage, the method comprising: receiving a regulator outputvoltage; converting said received output voltage into a digital errorsignal employing a delay line analog to digital converter (ADC); andadjusting said regulator output voltage based on said digital errorsignal.
 42. The method of claim 41 wherein said converting comprises:powering a delay cell array with said received converter output voltage;measuring a speed of test signal propagation through said powered delaycell array; and generating said digital error signal indicative of saidmeasured test signal propagation speed.
 43. The method of claim 42wherein said converting further comprises calibrating said delay lineADC.
 44. The method of claim 43 wherein said calibrating comprises:converting a reference voltage into a reference conversion error valueemploying said delay line ADC; and adding said reference conversionerror value to said digital error signal, thereby providing a correcteddigital error signal.
 45. The method of claim 43 wherein saidcalibrating comprises: powering said delay cell array with a referencevoltage; measuring a speed of test signal propagation through saidreference voltage-powered delay cell array; generating a referenceconversion error value indicative of said measured test signalpropagation speed; and adding said reference conversion error value tosaid generated digital error signal.
 46. The method of claim 41 whereinsaid adjusting comprises determining a digital control signal based onsaid generated digital error signal according to a control algorithm.47. A voltage controller comprising: a source of converter outputvoltage; an analog to digital converter (ADC) responsive to said outputvoltage to generate a digital error signal indicative of a differencebetween said output voltage and a previously stored reference voltage; adigital electronic calculator responsive to said digital error signal togenerate a digital control signal; and a pulse width modulatorresponsive to said generated digital control signal to generate apulse-on period for a power control signal; wherein said ADC includes adelay line.
 48. The voltage controller of claim 47 wherein said delayline ADC is responsive to a comparison between an active source ofreference voltage and said previously stored reference voltage togenerate a reference conversion error value.
 49. The voltage controllerof claim 48 wherein said delay line ADC comprises a register to storesaid reference conversion error value.
 50. The voltage controller ofclaim 49 wherein said delay line ADC further comprises a voltagecomparison circuit responsive to said digital error signal and saidreference conversion error value to generate a sum of said digital errorsignal and said reference conversion error value.
 51. (canceled)